1. Technical Field
Embodiments of the present invention generally relate to a power control device, and more particularly to a technology for cutting off an unnecessary leakage current path when power of an integrated circuit (IC) having heterogeneous power is ramped up.
2. Related Art
Generally, a power-up signal generation circuit of a semiconductor device indicates a circuit for initializing a semiconductor device. In order to operate the semiconductor device, the power-up signal generation circuit receives an external voltage (VDD) from an external part. The voltage level of the external voltage (VDD) starts from 0V and increases up to a target voltage level at a predetermined slope.
In this case, when all circuits of the semiconductor device directly receive the external voltage (VDD), the circuits need to initialize a specific node as well as to provide stable power. As a result, the semiconductor device includes a power-up signal generation circuit. The power-up signal generation circuit is used to enable a power-up signal, so that the external voltage (VDD) reaching a stable power level can be applied to respective circuits. The semiconductor device is initialized by the power-up operation.
FIG. 1 is a conceptual diagram illustrating a ramp-up operation of the external voltage (VDD) for use in a conventional integrated circuit (IC).
Referring to FIG. 1, the conventional IC has heterogeneous power-supply voltages (VDD1, VDD2). In this case, the external power-supply voltage VDD1 is higher than the external power-supply voltage VDD2.
During a predetermined period T1 of the ramp-up operation, the power-supply voltage VDD1 increases with a predetermined slope, reaches a target level, and is maintained at a predetermined voltage level. After lapse of the period T1, the power-supply voltage VDD2 increases with a predetermined slope. After lapse of a predetermined period T2, the power-supply voltage VDD2 reaches a target level, and is maintained at a predetermined voltage level.
However, before the power-supply voltage VDD1 is ramped up and the power-supply VDD2 is ramped up, an undesired leakage current occurs. That is, if the ramp-up time of the power-supply voltage VDD1 is different from the ramp-up time of the power-supply voltage VDD2, an unnecessary leakage current occurs. As described above, the power-supply voltage VDD2 is maintained at 0V before the power-supply voltages (VDD1, VDD2) are ramped up, so that an internal leakage current unavoidably occurs.